1. Field of the Invention
The present invention relates to an integrated circuit that is capable of suitably carrying out communications between chips such as IC (Integrated Circuit) bare chips to be stacked and mounted.
2. Description of the Related Arts
The present inventors have proposed electronic circuits that carry out communications by inductive coupling between chips to be stacked and mounted via coils formed by on-chip wiring of LSI (Large Scale Integration) chips (refer to Patent Literature 1).
FIG. 5 is a view depicting a configuration of a conventional (first) transmitter and receiver circuit. A part thereof is shown also in Patent Literature 1. FIG. 6 is a view depicting waveforms of respective portions of the circuit shown in FIG. 5. A transmitter circuit 300 is composed of a pulse generator 311, an inverter 312, a NOR circuit 313, transistors 314, 315, an inverter 316, a NOR circuit 317, transistors 318, 319, and a transmitter coil 320. The pulse generator 311 generates a pulse having a pulse width determined by a  propagation delay of an inverter delay line in synchronization with a rising edge of a transmission clock Txclk. The pulse is input to an H-bridge circuit, and if a transmission signal Txdata is high at the rising edge of the transmission clock Txclk, the H-bridge circuit allows a positive (arrow direction in the figure) pulse current IT (if the transmission signal Txdata is low, a negative pulse current IT) to flow through the transmitter coil 320. With this construction, a positive or negative triangular wave current IT flows through the transmitter coil 320 according to the transmission signal Txdata at the rising edge of the transmission clock Txclk.
A receiver circuit 350 is composed of a receiver coil 340, resistors 321, 322, transistors 323 to 332, NAND circuits 333, 334, and inverters 335, 336, and forms a comparator with a latch in its entirety. The receiver circuit 350 receives a receiving clock (synchronization signal) Rxclk externally and outputs receiving data Rxdata. The transistors 323, 324 constitute a differential pair of a differential amplifier, and receive a signal VR from the receiver coil 340. The NAND circuits 333, 334 form a latch. The data received by the differential amplifier is sampled in synchronization with the receiving clock Rxclk to be input into the transistors 323 to 325, 329, and 331, and latched by the NAND circuits 333, 334,  whereby the receiving signal Rxdata is restored.
This transmitter and receiver circuit is a synchronous type in which a system clock is used for reproduction of data. Accordingly, the data transfer rate is limited by the system clock.
Therefore, it has been proposed to synchronize high-speed data with timing pulses by independently having high-speed ring oscillators for generating timing pulses at the transmission side and the reception side, respectively, and sending signals to control the oscillation start/stop thereof parallel to transmitting data (refer to Non Patent Literature 1).
FIG. 7 is a view depicting a configuration of a conventional (second) transmitter and receiver circuit. FIG. 8 is a view depicting waveforms of respective portions of the circuit shown in FIG. 7. The transmission side is composed of a control circuit 411, an n-bit counter 412, a ring oscillator 413, a module (1) 414, and a 2n:1 multiplexer 415. The control circuit 411 operates based on an fHz system clock and supplies a reset pulse to the n-bit counter 412 (for example n=4). The n-bit counter 412 is reset by the reset pulse to make a timing signal Txstop as its MSB low, whereupon pulses are generated by the ring oscillator 413, and the n-bit counter 412 counts  the pulses. The n-bit counter 412, when the n-bit counter 412 counts 2n−1 (for example 8) pulses, makes the timing signal Txstop high to stop pulse generation by the ring oscillator 413. The 2n:1 multiplexer 415 multiplexes 2n (for example 16) parallel fb/s transmission data Mtxdata from the module (1) 414 2n times by rising and falling of a transmission timing pulse Txclk and transmits the multiplexed data as a 2n fb/s serial transmission signal Txdata.
The timing signal Txstop is transmitted by a non-chip wiring 421 from the transmission side to the reception side, and the transmission signal Txdata, by an on-chip wiring 422.
The reception side is composed of a ring oscillator 431, a 1:2n demultiplexer 432, and a module (2) 433. The ring oscillator 431 receives a timing signal Rxstop corresponding to the timing signal Txstop to generate a receiving timing pulse Rxclk, and supplies the same to the 1:2n demultiplexer 432. The 1:2n demultiplexer 432 receives a receiving signal Rxdata corresponding to the transmission signal Txdata, demultiplexes the same to 2n parallel fb/s receiving data Mrxdata by the receiving timing pulse Rxclk, and supplies the demultiplexed data to the module (2) 433.
However, while this technique is on the assumption that the respective ring oscillators have the same  characteristics, in different chips, ring oscillators on the respective chips greatly differ in characteristics due to manufacturing variations despite being of the same design, the difference in chips results in a difference in power supply voltage, and it is thus difficult to match the timing of pulses to be generated by the ring oscillator in each chip, and this technique is not suitable for communications between chips.
FIG. 9 is a view depicting a configuration of a reference (third) transmitter and receiver circuit. This is an example where a transmitter chip 500 and a receiver chip are connected by wiring therebetween, and a multiplexed signal and a timing pulse of multiplication are respectively transmitted from the transmitter chip 500 to the receiver chip to perform demultiplexing in the receiver chip 550. The transmitter chip 500 is composed of a PLL (Phase Locked Loop) and a 2n:1 multiplexer 515. The PLL 510 is composed of a PFD (Phase Frequency Detector) 511, a CP (Charge Pump) 512, a VCO (Voltage Controlled Oscillator) 513, and a ½n-1 frequency divider 514, and generates a 2n−1 fHz transmission timing pulse Txclk from an fHz system clock and supplies the same to the 2n:1 multiplexer 515. The 2n:1 multiplexer 515 multiplexes 2n parallel fb/s transmission data Mtxdata 2n times by the transmission timing pulse Txclk and transmits the multiplexed  data as a 2nfb/s serial transmission signal Txdata.
The transmission timing pulse Txclk is transmitted by an interchip wiring 521 from the transmitter chip 500 to the receiver chip 550, and the transmission signal Txdata, by an interchip wiring 522.
The receiver chip 550 is composed of a 1:2n demultiplexer 531, which receives a receiving timing pulse Rxclk corresponding to the transmission timing pulse Txclk, and demultiplexes a 2nfb/s serial receiving signal Rrxdata into 2n parallel fb/s receiving data Mrxdata.
However, this method can be used for transmission of a continuous clock whose oscillation frequency has been controlled at high accuracy in the PLL, but is not suitable for transmission of a predetermined number of pulses generated by a ring oscillator etc.
FIG. 10A and FIG. 10B are views for comparing two types of pulse trains. FIG. 10A depicts a pulse train by a PLL, and FIG. 10B depicts a pulse train by a ring oscillator. As shown in FIG. 10A, a continuous clock ClkPLL generated in the PLL has been controlled in oscillation frequency with accuracy and thus has less jitter. On the other hand, a pulse train ClkRING of a predetermined number of pulses generated in the ring oscillator of a simpler configuration than the PLL  is not stabilized in oscillation frequency, has a large amount of jitter, and contains a higher frequency component than that of the continuous clock ClkPLL. In the data transmission technology shown in FIG. 9, due to a band limitation of the interchip wiring, a high frequency component is cut in the course of transmission, so that the jitter of the pulse train ClkRING changes. Therefore, phase information of the pulse train ClkRING when being multiplexed is lost, erroneous phase information is transmitted to the 1:2n demultiplexer 531, so that demultiplexing cannot be correctly performed.
FIG. 11 is a view depicting a configuration of a conventional (fourth) transmitter and receiver circuit. A part thereof is shown also in Patent Literature 2. FIG. 12 is a view depicting waveforms of respective portions of the circuit shown in FIG. 11. A transmitter circuit 700 is composed of transistors 711 to 714, a delay line 715, and a transmitter coil 716. A receiver circuit 750 is composed of a receiver coil 721 and transistors 722 to 727.
This is an example where, when logic of a transmission signal Txdata transits, a positive or negative pulse current IT flows through the transmitter coil 716, and the receiver circuit 750 restores receiving data Rxdata, as a result of, by inverting data upon a latter-half pulse while ignoring a  first-half pulse of a double pulse of a received voltage VR with using a change in threshold value due to latching of a hysteresis comparator. This enables asynchronous inductive coupling communication.
[Patent Literature 1] US 20070289772 A1
[Patent Literature 2] JP 2006-050354 A
[Non Patent Literature 1] S. Kimura et al., “An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators,” In Proc. of International Solid-State Circuits Conference (ISSCC2003), pp. 390-391, February 2003.